1. Field of the Invention
This invention relates to microprocessor circuitry and, more particularly, to the generation of internal microprocessor clock signals.
2. Description of the Relevant Art
Microprocessor circuits require clock signals to provide timing references for controlling activities within the microprocessor. A microprocessor typically receives an external clock signal generated by a crystal oscillator or other external clock source and, using this external clock signal, generates an internal clock signal having a high degree of stability with a fifty-percent duty cycle. The internally generated clock signal may have the same frequency as that of the external clock signal or may have a frequency that is a fraction or a multiple of the external clock signal frequency.
CMOS integrated circuit microprocessors, for proper operation thereof, generally must be clocked by an internal clock signal having a first phase and a second phase for each clock cycle period. The clock signal first phase is at a high level for a first execution time period and the second phase is at a low level for a second execution time period to complete each clock cycle. The reason for this clocking procedure is that CMOS integrated circuits include circuitry wherein a first portion of the circuitry is active during the high level first phase of the clock signal and the other portion of the circuitry is active during the low level second phase of the clock signal. For this reason, the microprocessor typically generates a pair of internal clock signals that are 180 degrees out of phase, one being provided to the first portion of the circuitry and the second being provided to the other portion of the circuitry.
The first and second phases of each clock signal cycle must be of sufficient duration to enable both portions of the microprocessor circuitry to complete their execution. Each such portion requires some finite minimum execution time because of internal microprocessor delays resulting from internal speed paths. To ensure that the minimum execution times are met for both portions of the microprocessor circuitry while maximizing the frequency of the internal clock signals, the duty cycles of the internal clock signals are typically regulated and maintained at fifty percent.
In addition to the foregoing, the internal speed paths and resulting first and second minimum execution time periods are greatly affected by integrated circuit processing parameters, microprocessor operating temperature, and microprocessor operating supply voltage. For example, microprocessors execute more slowly as operating temperature increases. Microprocessors also execute more slowly as the operating supply voltage decreases. In either or both of these cases, the duration of the first and second clock signal phases must be extended to provide first and second execution times which are sufficient to accommodate the increased first and second minimum execution time periods.
Clock generators for providing such clock signals are generally provided "on chip" in CMOS microprocessor devices. However, as stated previously, they develop the clock signal or signals in response to an input clock signal generated by an external clock source. The on chip clock generator must be arranged to provide the clock signal first and second phases because external clock sources cannot always be relied upon to provide the clock signals accurately. In fact, external clock sources usually provide input clock signals having a duty cycle in a wide range. It is therefore required that the on chip clock generator be able to derive the clock signals for clocking the microprocessor responsive to an input clock signal having a wide range of duty cycles.
In addition to providing internal clock signals that are 180 degrees out of phase with duty cycles of fifty percent, there are several other important considerations associated with the generation of such clock signals. On the semiconductor die itself, a single on chip clock generator is typically situated near the center of the microprocessor chip. The drive strength requirements of this internal clock generator depends upon the type and amount of other circuitry fabricated on the microprocessor die, as well as the routing of the clock signals. In general, as the circuitry incorporated on the microprocessor die becomes more complex and voluminous, the greater the required drive strength of the internal clock generator. This can adversely affect electromagnetic interference (EMI).
Electromagnetic interference is generated by nearly all electrical circuits. The quantity of EMI radiated by a microprocessor circuit is based upon many factors, including the current transitions generated by the clocks and other logic circuits driven by the clocks. In general, the circuits on the semiconductor chip are a source of the transient currents, and the surrounding components such as the device package, the printed circuit board, and the cables attached to the printed circuit board act as antennae that radiate the high frequency components of the transient currents.
EMI can radiate in one of two modes: common mode and differential mode. Differential mode radiation occurs when time-varying current loops exist on a PC board or similar structure. Common mode radiation is basically a uniform flow of current through, for example, a monopole antenna.
Current loops of high frequency current are set up in the vicinity of microprocessors due to on-chip clock circuits. This is because the current drive source for the clock drivers are often localized while the return path for the current (through the load on the clock signals, which is a distributed capacitance) is more uniformly distributed. The current drive source is not generally uniform because the clock drivers are sometimes on isolated power supplies on the chip, because the clock driver is closer to one side of the chip, or because of some other asymmetry in the power supply pins to the microprocessor.
The transient currents and therefore the EMI generated by the internal clock generator of a microprocessor can be excessively large for a number of reasons. First, as the circuit complexity of microprocessors has grown during the past years, so have the drive requirements of the internal clock generator. The driver transistors within the internal clock generator have therefore been required to source and sink increasingly larger current levels. This has led to significant increases in the generated EMI due to the large current that is sourced or sunk at a given location on the semiconductor die.
Another reason electromagnetic interference can become excessive is that the internal clock generator is designed to satisfy the drive requirements during worst-case conditions. As a consequence, the clock generator is significantly over-driven during normal operating conditions, thus resulting in increased electromagnetic interference.
Chip manufacturers typically control EMI emission through package design techniques. These techniques include power/ground planes within the package, grounded seal lids, and rails for by-pass capacitors. Systems manufacturers typically use board-level and enclosure techniques including moating in the PC board, separate power-ground planes, chokes, decoupling capacitors, and shielding. Many of these techniques are relatively expensive to employ.
EMI reduction is a rather important feature for manufacturers who would like to comply with FCC Class B and other requirements. Compliance with FCC Class B allows the device to be used in either a residential or a commercial application. Class A is restricted to industrial use only. Thus, a product that conforms to Class B will include a much larger market.
The internal clock frequency is also an important consideration with respect to the generation of internal microprocessor clock signals. In general, as the speed of the internal microprocessor clock increases, the time required to execute a particular program decreases. Thus, microprocessors having relatively high internal clock frequencies are desirable for high performance and computational-intensive applications. On the other hand, relatively fast microprocessors are usually more expensive than slower microprocessors, both in design and manufacture. Furthermore, a microprocessor operating at higher speeds typically consumes more power in comparison to their lower speed counterparts. The frequency and edge rate (slew rate) of the internal clock signals also affect the EMI emissions significantly.
As a result of these tradeoffs of generated EMI, performance, and cost, microprocessor manufacturers commonly provide versions of the same microprocessor family that meet different EMI, power and speed targets; one version that operates at a relatively high speed for high performance and computational-intensive applications, and another version that operates at a lower speed for low EMI and low power applications. To provide these differing versions, the microprocessor is typically fabricated with two separate clock generators incorporated on the semiconductor die. Mask programming methods can be employed during the fabrication of the microprocessor to enable one of the clock generators and disable the other clock generator. Unfortunately, this technique is somewhat expensive since a different set of masks must be used for the different microprocessor versions and, in addition, considerable die space is wasted since one of the clock generators on the semiconductor die is permanently disabled. Furthermore, once the microprocessor chip has been fabricated for use with a crystal oscillator of a predetermined maximum frequency, the internal maximum clock frequency cannot be changed.